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1 datasheet 40v radiation hardened and set enhanced precision low power operational amplifier ISL70219ASEH, isl70419aseh the ISL70219ASEH and isl70419aseh are a family of very high precision amplifiers featuring the perfect combination of low noise vs power consumption. low offset voltage, low i bias current and low temperature drift making them the ideal choice for applications requiring both high dc accuracy and ac performance. the combination of high precision, low noise, low power and small footprint provides the user with outstanding value and flexibility relative to similar competitive parts. applications for these amplifiers include precision active filters, medical and analytical instrumentation, precision power supply controls and industrial controls. the ISL70219ASEH is offered in a 10 lead hermetic ceramic flatpack. the isl70419aseh is offered in a 14 lead hermetic ceramic flatpack package. the devices are packaged in industry standard pin configur ations and operate across the extended temperature range from -55c to +125c. related literature ? ug007 , ?ISL70219ASEH evaluation board user guide? ? tr002 , ?single event effects (see) testing of the ISL70219ASEH dual operational amplifier? ? ISL70219ASEH smd 5962-14226 ? ISL70219ASEH radiation test report features ? electrically screened to dla smd# 5962-14226 ? low input offset voltage. . . . . . . . . . . . . . . . . . . .110v, max ? superb offset temperature coefficient. . . . . . . . 1v/c, max ? input bias current . . . . . . . . . . . . . . . . . . . . . . . . . .15na, max ? input bias current tc . . . . . . . . . . . . . . . . . . . . 5pa/c, max ? low current consumption . . . . . . . . . . . . . . . . . . . . . . . 440a ? voltage noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8nv/ hz ? wide supply range . . . . . . . . . . . . . . . . . . . . . . . . . .4.5v to 36v ? operating temperature range. . . . . . . . . . . .-55c to +125c ?radiation environment - seb let th (v s = 18v) . . . . . . . . . . . . . .86.4 mev?cm 2 /mg - set recovery time . . . . . . . . . . . 10s at 60 mev?cm 2 /m - sel immune (soi process) - total dose hdr (50 to 300rad(si)/s). . . . . . . . 300krad(si) - total dose ldr (10mrad(si)/s) . . . . . . . . . . . 100krad(si) * * product capability established by initial characterization. the eh version is acceptance tested on a wafer-by-wafer basis to 50krad(si) at low dose rate. applications ? precision instrumentation ? spectral analysis equipment ? active filter blocks, thermocouples and rtd reference buffers ? data acquisition and power supply control figure 1. typical application: sallen-key low pass filter (f c = 10khz) figure 2. set deviation vs duration for let = 60 mev?cm 2 /mg ( v s = 18v) - + output v + r 1 v - r 2 c 1 c 2 v in 1.84k 4.93k 3.3nf 8.2nf isl70x19aseh 0 2 4 6 8 10 12 14 16 -8 -6 -4 -2 0 2 4 set duration (s) set extreme deviation (v) october 27, 2014 fn8459.0 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2014. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
ISL70219ASEH, isl70419aseh 2 fn8459.0 october 27, 2014 submit document feedback pin configurations ISL70219ASEH (10 ld flatpack) top view isl70419aseh6 (14 ld flatpack) top view pin descriptions 10 ld pin number 14 ld pin number pin name equivalent esd circuit description 11out a circuit 2 amplifier a output 22-in a circuit 1 amplifier a inverting input 3 3 +in a circuit 1 amplifier a noninverting input 10 4 v + circuit 3 positive power supply 7 5 +in b circuit 1 amplifier b noninverting input 86-in b circuit 1 amplifier b inverting input 97out b circuit 2 amplifier b output -8out c circuit 2 amplifier c output -9-in c circuit 1 amplifier c inverting input -10+in c circuit 1 amplifier c noninverting input 511 v - circuit 3 negative power supply -12+in d circuit 1 amplifier d noninverting input -13-in d circuit 1 amplifier d inverting input -14out d circuit 2 amplifier d output - e-pad e-pad none e-pad under package (unbiased, tied to package lid) 4- nc -no connect 6 - lid na unbiased, tied to package lid 10 9 8 7 6 2 3 4 5 1 out a -in a +in a nc v - v + out b -in b +in b lid + - + - a b -+ - + -+ - + bc ad out a -in a +in a v + 1 2 3 4 5 6 7 10 9 8 11 12 13 14 +in b -in b out b v - +in c -in c out c out d -in d +in d circuit 2 circuit 1 v + v - circuit 3 capacitively coupled esd clamp in- v + v - in+ 500 500 v + v - out
ISL70219ASEH, isl70419aseh 3 fn8459.0 october 27, 2014 submit document feedback ordering information ordering/smd number ( note 2 ) part number ( note 1 ) temp range (c) package (rohs compliant) pkg. dwg. # 5962f1422602vyc ISL70219ASEHvf -55 to +125 10 ld flatpack k10.a 5962f1422602v9a ISL70219ASEHvx -55 to +125 die ISL70219ASEHf/proto ISL70219ASEHf/proto -55 to +125 10 ld flatpack k10.a ISL70219ASEHf/sample ISL70219ASEHvx/sample -55 to +125 die 5962f1422603vxc ( coming soon ) isl70419asehvf -55 to +125 14 ld flatpack k14.c 5962f1422603v9a ( coming soon ) isl70419asehvx -55 to +125 die isl70419asehf/proto ( coming soon ) isl70419asehf/proto -55 to +125 14 ld flatpack k14.c isl70419asehf/sample ( coming soon ) isl70419asehvx/sample -55 to +125 die ISL70219ASEHev1z ISL70219ASEHev1z evaluation board isl70419asehev1z (coming soon) isl 70419asehev1z evaluation board notes: 1. these intersil pb-free hermetic packaged products employ 100% au plate - e4 termination finish, which is rohs compliant and c ompatible with both snpb and pb-free soldering operations. 2. specifications for rad hard qml devices are controlled by the defense logistics agency land and maritime (dla). the smd numbe rs listed in the ?ordering information? table must be used when ordering.
ISL70219ASEH, isl70419aseh 4 fn8459.0 october 27, 2014 submit document feedback absolute maximum ratings thermal information maximum supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42v maximum supply voltage ( note 5 ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36v maximum differential input current . . . . . . . . . . . . . . . . . . . . . . . . . . 20ma maximum differential input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20v min/max input voltage . . . . . . . . . . . . . . . . . . . . . . . . . v - - 0.5v to v + + 0.5v max/min input current for input voltage >v + or ISL70219ASEH, isl70419aseh 5 fn8459.0 october 27, 2014 submit document feedback v ol output voltage low r l = 10k to ground - -16.7 -16.5 v -- -16.2 v r l = 2k to ground - -16.5 -16.3 v -- -16.0 v i s supply current/amplifier - 0.49 0.725 ma -- 0.85 ma i sc output short-circuit current sourcing: v in = 0v, v out = -16v ( note 7 ) -41- ma sinking: v in = 0v, v out = +16v ( note 7 ) --42 ma v supply supply voltage range guaranteed by psrr 2.25 - 20 v ac specifications gbwp gain bandwidth product a v = 1k, r l = 2k ( note 7 )-1.5-mhz e nvp-p voltage noise v p-p 0.1hz to 10hz ( note 7 ) - 0.25 - v p-p e n voltage noise density f = 10hz ( note 7 )-10-nv/ hz e n voltage noise density f = 100hz ( note 7 ) - 8.2 - nv/ hz e n voltage noise density f = 1khz ( note 7 ) - 8 - nv/ hz e n voltage noise density f = 10khz ( note 7 )-8-nv/ hz i n current noise density f = 1khz ( note 7 ) - 0.1 - pa/ hz transient response sr slew rate, v out 20% to 80% a v = 1, r l = 2k ?? v o = 4v p-p 0.3 0.5 - v/s 0.2 --v/s t r , t f , small signal rise time 10% to 90% of v out a v = 1, v out = 50mv p-p , r l = 10k ? to v cm - 130 450 ns -- 625 ns fall time 90% to 10% of v out a v = 1, v out = 50mv p-p , r l = 10k ? to v cm - 130 600 ns -- 700 ns t s settling time to 0.1% 10v step; 10% to v out a v = -1, v out = 10v p-p , r l = 5k ? to v cm ( note 7 ) -21- s settling time to 0.01% 10v step; 10% to v out a v = -1, v out = 10v p-p , r l = 5k ? to v cm ( note 7 ) -24- s settling time to 0.1% 4v step; 10% to v out a v = -1, v out = 4v p-p , r l = 5k ? to v cm ( note 7 ) -13- s settling time to 0.01% 4v step; 10% to v out a v = -1, v out = 4v p-p , r l = 5k ? to v cm ( note 7 ) -18- s t ol output positive overload recovery time a v = -100, v in = 0.2 v p-p, r l = 2k ? to v cm ( note 7 ) -5.6- s output negative overload recovery time a v = -100, v in = 0.2 v p-p, r l = 2k ? to v cm ( note 7 ) - 10.6 - s os+ positive overshoot a v = 1, v out = 10v p-p , r f = 0 r l =2k ? to v cm -15- % -- 33 % os- negative overshoot a v = 1, v out = 10v p-p , r f = 0 r l =2k ? to v cm -15- % -- 33 % electrical specifications v s = 18.0v, v cm = v o = 0v, r l = open, t a = +25c, unless otherwise noted. boldface limits apply acro ss the operating temperature range, -55c to +125c; over a total ionizing dose of 300k rad(si) with exposure at a high dose rate of 50 to 300rad(si)/s or ov er a total ionizing dose of 50krad(si) with exposure at a low dose rate of <10mrad( si)/s, unless otherwise noted . (continued) parameter description test conditions min ( note 6 )typ max ( note 6 )units
ISL70219ASEH, isl70419aseh 6 fn8459.0 october 27, 2014 submit document feedback electrical specifications v s = 5.0v, v cm = v o = 0v, r l = open, t a = +25c, unless otherwise noted. boldface limits apply across the operating temperature range, -55c to +125c; over a total ionizing dose of 300krad(si) with exposure at a high dose rate of 50 to 300rad(si)/s or over a total ionizing dose of 50krad(si) with ex posure at a low dose rate of <10mrad(si)/s, unless otherwise no ted. parameter description test conditions min ( note 6 )typ max ( note 6 )units v os input offset voltage - 10 150 v - - 250 v tcv os offset voltage drift ( note 7 ) - 0.1 1 v/ c i b input bias current t a = +25c -2.5 0.08 2.5 na t a = -55c, +125c -5 - 5 na t a = +25c, post hdr/ldr rad -15 - 15 na tci b input bias current temperature coefficient ( note 7 ) -5 1 5 pa/c i os input offset current t a = +25c -2.5 0.3 2.5 na t a = -55c, +125c -3 - 3 na t a = +25c, post hdr/ldr rad -10 - 10 na tci os input offset current temperature coefficient ( note 7 ) -3 0.42 3 pa/c v cm input voltage range guaranteed by cmrr test -3 3 v cmrr common-mode rejection ratio v cm = -3v to +3v 120 145 db 120 db psrr power supply rejection ratio v s = 2.25v to 5v 120 145 db 120 db a vol open-loop gain v o = -3.0v to +3.0v r l = 10k to ground 3,000 14,000 v/mv v oh output voltage high r l = 10k to ground 3.5 3.7 v 3.2 v r l = 2k to ground 3.3 3.55 v 3.0 v v ol output voltage low r l = 10k to ground -3.7 -3.5 v -3.2 v r l = 2k to ground -3.55 -3.3 v -3.0 v i s supply current/amplifier 0.47 0.675 ma 0.8 ma ac specifications gbwp gain bandwidth product a v = 1k, r l = 2k ( note 7 ) 1.5 mhz e nvp-p voltage noise v p-p 0.1hz to 10hz ( note 7 ) - 0.25 - v p-p e n voltage noise density f = 10hz ( note 7 )-12-nv/ hz e n voltage noise density f = 100hz ( note 7 )-8.6-nv/ hz e n voltage noise density f = 1khz ( note 7 ) - 8 - nv/ hz e n voltage noise density f = 10khz ( note 7 )-8-nv/ hz i n current noise density f = 1khz ( note 7 ) - 0.1 - pa/ hz
ISL70219ASEH, isl70419aseh 7 fn8459.0 october 27, 2014 submit document feedback transient response sr slew rate, v out 20% to 80% a v = 1, r l = 2k ?? v o = 4v p-p ( note 7 ) -0.5- v/s t r , t f , small signal rise time 10% to 90% of v out a v = 1, v out = 50mv p-p , r l = 10k ? to v cm ( note 7 ) - 130 - ns fall time 90% to 10% of v out a v = 1, v out = 50mv p-p , r l = 10k ? to v cm ( note 7 ) - 130 - ns t s settling time to 0.1% 4v step; 10% to v out a v = -1, v out = 4v p-p , r l = 5k ? to v cm ( note 7 ) -12- s settling time to 0.01% 4v step; 10% to v out a v = -1, v out = 4v p-p , r l = 5k ? to v cm ( note 7 ) -19- s t ol output positive overload recovery time a v = -100, v in = 0.2 v p-p, r l = 2k ? to v cm ( note 7 ) -7- s output negative overload recovery time a v = -100, v in = 0.2 v p-p, r l = 2k ? to v cm ( note 7 ) -5.8- s os+ positive overshoot a v = 1, v out = 10v p-p , r f = 0 r l =2k ? to v cm (v) -15- % os- negative overshoot a v = 1, v out = 10v p-p , r f = 0 r l =2k ? to v cm ( note 7 ) -15- % electrical specifications v s = 2.25v, v cm = v o = 0v, r l = open, t a = +25c, unless otherwise noted. boldface limits apply across the operating temperat ure range, -55c to +125c; over a total ionizing dose of 300krad(si) with exposure at a high dose rate of 50 to 300rad(si)/s or over a total ionizing do se of 50krad(si) with exposure at a low do se rate of <10mrad(si)/s, unless otherwise noted. parameter description test conditions min ( note 6 )typ max ( note 6 )units v os input offset voltage 10 150 v 250 v tcv os offset voltage drift ( note 7 )0.1 1 v/ c i b input bias current t a = +25c -2.5 0.18 2.5 na t a = -55c, +125c -5 - 5 na t a = +25c, post hdr/ldr rad -15 - 15 na tci b input bias current temperature coefficient ( note 7 ) -5 1 5 pa/c i os input offset current t a = +25c -2.5 0.3 2.5 na t a = -55c, +125c -3 - 3 na t a = +25c, post hdr/ldr rad -10 - 10 na tci os input offset current temperature coefficient ( note 7 ) -3 0.42 3 pa/c v cm input voltage range guaranteed by cmrr test -0.25 0.25 v cmrr common-mode rejection ratio v cm = -0.25v to +0.25v 90 110 db 90 db electrical specifications v s = 5.0v, v cm = v o = 0v, r l = open, t a = +25c, unless otherwise noted. boldface limits apply across the operating temperature range, -55c to +125c; over a total ionizing dose of 300krad(si) with exposure at a high dose rate of 50 to 300rad(si)/s or over a total ionizing dose of 50krad(si) with ex posure at a low dose rate of <10mrad(si)/s, unless otherwise no ted. (continued) parameter description test conditions min ( note 6 )typ max ( note 6 )units
ISL70219ASEH, isl70419aseh 8 fn8459.0 october 27, 2014 submit document feedback v oh output voltage high r l = 10k to ground 0.8 1.03 v 0.5 v r l = 2k to ground 0.75 0.98 v 0.45 v v ol output voltage high r l = 10k to ground -1.03 -0.8 v -0.5 v r l = 2k to ground -0.98 -0.75 v -0.45 v notes: 6. compliance to datasheet limits is assu red by one or more methods: production test, characterization and/or design. 7. guaranteed by characterization, not tested. electrical specifications v s = 2.25v, v cm = v o = 0v, r l = open, t a = +25c, unless otherwise noted. boldface limits apply across the operating temperat ure range, -55c to +125c; over a total ionizing dose of 300krad(si) with exposure at a high dose rate of 50 to 300rad(si)/s or over a total ionizing do se of 50krad(si) with exposure at a low do se rate of <10mrad(si)/s, unless otherwise noted. parameter description test conditions min ( note 6 )typ max ( note 6 )units
ISL70219ASEH, isl70419aseh 9 fn8459.0 october 27, 2014 submit document feedback typical performance curves unless otherwise specified, v s 18v, v cm = 0, v o = 0v, t a = +25c. figure 3. v os vs temperature (18v) figure 4. v os vs temperature (5v) figure 5. v os vs temperature (2.5v) figure 6. i bias vs temperature figure 7. i bias vs temperature (5v) figure 8. i bias vs temperature (2.5v) -100 -80 -60 -40 -20 0 20 40 -75 -25 25 75 125 175 offset voltage (v) temperature (c) -100 -80 -60 -40 -20 0 20 40 -75 -25 25 75 125 175 offset voltage (v) temperature (c) -100 -80 -60 -40 -20 0 20 40 -75 -25 25 75 125 175 offset voltage (v) temperature (c) -0.4 -0.35 -0.30 -0.25 -0.20 -0.15 -0.10 -0.05 0 0.05 -75 -25 25 75 125 175 bias current (na) temperature (c) -0.1 -0.05 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 -75 -25 25 75 125 175 bias current (na) temperature (c) -0.2 -0.1 0 0.1 0.2 0.3 0.4 -75 -25 25 75 125 175 bias current (na) temperature (c)
ISL70219ASEH, isl70419aseh 10 fn8459.0 october 27, 2014 submit document feedback figure 9. offset current vs temperature figure 10. supply current vs temperature figure 11. av ol vs temperature (v o = 13v) figure 12. psrr vs temperature (2.25v to 20v) figure 13. cmrr vs temperature figure 14. i sc vs temperature typical performance curves unless otherwise specified, v s 18v, v cm = 0, v o = 0v, t a = +25c. (continued) 0.5 0.55 0.60 0.65 0.70 0.75 0.80 -75 -25 25 75 125 175 offset current (na) temperature (c) 18v 5.0v 2.5v 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 -75 -25 25 75 125 175 supply current (ma) temperature (c) 18v 5.0v 2.5v temperature (c) -75 -50 -25 0 25 50 75 100 125 150 av ol (v/mv) 10000 15000 20000 25000 temperature (c) psrr (db) -70 -50 -30 -10 10 30 50 70 90 110 130 -145 -140 -135 temperature (c) -75 -50 -25 0 25 50 75 100 125 150 cmrr (db) -160 -155 -150 -145 -140 -135 -130 0 10 20 30 40 50 60 70 -75 -25 25 75 125 175 supply current (ma) temperature (c) 18v 5.0v 2.5v
ISL70219ASEH, isl70419aseh 11 fn8459.0 october 27, 2014 submit document feedback figure 15. v os vs vcm (18v) figure 16. v oh vs temperature (r l = 2k) figure 17. v oh vs temperature (r l = 5k) figure 18. v oh vs temperature (r l = 10k) figure 19. v ol vs temperature (r l = 2k) figure 20. v ol vs temperature (r l = 5k) typical performance curves unless otherwise specified, v s 18v, v cm = 0, v o = 0v, t a = +25c. (continued) -100 -80 -60 -40 -20 0 20 40 60 80 100 0 5 10 15 20 25 30 35 40 offset voltage (v) common mode voltage (v) -55c +25c +125c 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 -75 -25 25 75 125 175 v oh (v) temperature (c) 18v 5.0v 2.5v 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 -75 -25 25 75 125 175 temperature (c) 18v 5.0v 2.5v v oh (v) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 -75 -25 25 75 125 175 temperature (c) 18v 5.0v 2.5v v oh (v) 0 0.5 1.0 1.5 2.0 2.5 -75 -25 25 75 125 175 temperature (c) 18v 5.0v 2.5v v ol (v) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 -75 -25 25 75 125 175 temperature (c) 18v 5.0v 2.5v v ol (v)
ISL70219ASEH, isl70419aseh 12 fn8459.0 october 27, 2014 submit document feedback figure 21. v ol vs temperature (r l = 10k) figure 22. input noise voltage (0.1hz to 10hz) figure 23. input noise voltage spectral density f igure 24. input noise cu rrent spectral density figure 25. open-loop gain , phase vs frequency (r l =10k ? ?? c l =10pf) figure 26. open loop frequency response (r l = 10k ? , c l = 100pf) typical performance curves unless otherwise specified, v s 18v, v cm = 0, v o = 0v, t a = +25c. (continued) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 -75 -25 25 75 125 175 temperature (c) 18v 5.0v 2.5v v ol (v) time (s) input noise voltage (nv) 012345678910 -250 -200 -150 -100 -50 0 50 100 150 200 250 v + = 36.4v r g = 10, r f = 100k a v = 10,000 frequency (hz) 1 10 100 1 10 100 1k 10k 100k input noise voltage (nv/ hz) v s = 18.2v a v = 1 frequency (hz) 1 10 100 1k 10k 100k 1 input noise current (pa/ hz) 0.1 v s = 18.2v a v = 1 open loop gain (db)/phase () frequency (hz) -100 -80 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 200 0.1m 1m 10m 100m 1 10 100 1k 10k 100k 1m 10m 100m r l = 10k simulation c l = 10pf gain phase open loop gain (db)/phase () frequency (hz) -100 -80 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 200 0.1m 1m 10m 100m 1 10 100 1k 10k 100k 1m 10m 100m r l = 10k simulation c l = 100pf gain phase
ISL70219ASEH, isl70419aseh 13 fn8459.0 october 27, 2014 submit document feedback figure 27. cmrr vs supply voltage (+25c) figure 28. psrr vs supply voltage (+25c) figure 29. frequency response vs acl (2.5v) f igure 30. frequency response vs acl (5.0v) figure 31. frequency response vs acl (18.0v) figure 32. frequency response vs feedback resistance (2.5v) typical performance curves unless otherwise specified, v s 18v, v cm = 0, v o = 0v, t a = +25c. (continued) -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 1 10 100 1k 10k 100k 1m 10m cmrr (db) frequency (hz) 5v 2.5 18v -120 -100 -80 -60 -40 -20 0 1 10 100 1k 10k 100k 1m 10m psrr (db) frequency (hz) 5v 2.5 18v -60 -40 -20 0 20 40 60 80 100 1k 10k 100k 1m 10m gain (db) frequency (hz) acl1 acl10 acl100 acl1000 -60 -40 -20 0 20 40 60 80 100 1k 10k 100k 1m 10m gain (db) frequency (hz) acl1 acl10 acl100 acl1000 -60 -40 -20 0 20 40 60 80 100 1k 10k 100k 1m 10m gain (db) frequency (hz) acl1 acl10 acl100 acl1000 -10 -8 -6 -4 -2 0 2 4 1k 10k 100k 1m 10m normalized gain (db) frequency (hz) rf = rg = 100 rf = rg = 1k rf = rg = 10k rf = rg = 100k
ISL70219ASEH, isl70419aseh 14 fn8459.0 october 27, 2014 submit document feedback figure 33. frequency response vs feedback resistance (5.0v) figure 34. frequency response vs feedback resistance (18.0v) figure 35. frequency response vs r l (2.5v) figure 36. frequency response vs r l (5.0v) figure 37. frequency response vs r l (18.0v) figure 38. frequency response vs c l (2.5v) typical performance curves unless otherwise specified, v s 18v, v cm = 0, v o = 0v, t a = +25c. (continued) -10 -8 -6 -4 -2 0 2 4 1k 10k 100k 1m 10m normalized gain (db) frequency (hz) rf = rg = 100 rf = rg = 1k rf = rg = 100k rf = rg = 10k -10 -8 -6 -4 -2 0 2 4 1k 10k 100k 1m 10m normalized gain (db) frequency (hz) rf = rg = 100 rf = rg = 1k rf = rg = 100k rf = rg = 10k -10 -8 -6 -4 -2 0 2 4 1k 10k 100k 1m 10m gain (db) frequency (hz) r l = 100 r l = 500 r l = 5k r l = 10k r l = 1k -10 -8 -6 -4 -2 0 2 4 1k 10k 100k 1m 10m frequency (hz) r l =100 r l = 500 r l = 5k r l = 10k gain (db) r l = 1k -10 -8 -6 -4 -2 0 2 4 1k 10k 100k 1m 10m gain (db) frequency (hz) r l = 100 r l = 500 r l = 5k r l = 10k r l = 1k -10 -8 -6 -4 -2 0 2 4 6 8 10 1k 10k 100k 1m 10m gain (db) frequency (hz) c l = 4pf c l = 43pf c l = 150pf c l = 220pf c l = 470pf c l = 1000pf
ISL70219ASEH, isl70419aseh 15 fn8459.0 october 27, 2014 submit document feedback figure 39. frequency response vs c l (5.0v) figure 40. frequency response vs c l (18.0v) figure 41. frequency respon se vs supply voltage (+25c) figure 42. crosstalk (+25c) figure 43. small signal transient response (+25c) f igure 44. large signal transient response (+25c) typical performance curves unless otherwise specified, v s 18v, v cm = 0, v o = 0v, t a = +25c. (continued) -10 -8 -6 -4 -2 0 2 4 6 8 10 1k 10k 100k 1m 10m gain (db) frequency (hz) c l = 4pf c l = 470pf c l = 1000pf c l = 220pf c l = 43pf c l = 150pf -10 -8 -6 -4 -2 0 2 4 6 8 10 1k 10k 100k 1m 10m gain (db) frequency (hz) c l = 4pf c l = 43pf c l = 150pf c l = 220pf c l = 470pf c l = 1000pf -10 -8 -6 -4 -2 0 2 1k 10k 100k 100m 10m gain (db) frequency (hz) v s = 19.8v v s = 2.25v v s = 16.2v v s = 2.75v v s = 18v v s = 5v v s = 5.5v v s = 4.5v v s = 2.5v 0 20 40 60 80 100 120 140 160 180 10 100 1k 10k 100k 1m 10m frequency (hz) crosstalk (db) v s = 15v r l -driver ch. = open a v = +1 v source = 1v p-p c l = 4pf r l -receiving ch. = 10k time (s) small signal t ransient r esponse (mv) -10 0 10 20 30 40 50 60 0 5 10 15 20 25 30 35 40 r l = 10k a v = +1 c l = 4pf v out = 50mv p-p v s =5, 18v time (s) large signal transient response (v) -2.4 -2.0 -1.6 -1.2 -0.8 -0.4 0 0.4 0.8 1.2 1.6 2.0 2.4 0 102030405060708090100 a v = +1 c l = 4pf v out = 4v p-p v s = 5v, r l = 2k, 10k v s = 18v, r l = 2k, 10k
ISL70219ASEH, isl70419aseh 16 fn8459.0 october 27, 2014 submit document feedback figure 45. slew rate vs temperature v s = 2.5 figure 46. slew rate vs temperature v s = 5v figure 47. slew rate vs temperature v s = 18v figure 48. overshoot + vs capacitance figure 49. overshoot - vs capacitance figure 50. output overdrive response vs temperature typical performance curves unless otherwise specified, v s 18v, v cm = 0, v o = 0v, t a = +25c. (continued) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 -75 -50 -25 0 25 50 75 100 125 150 temperature (c) slew rate (v/s) positive slew rate negative slew rate 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 -75 -50 -25 0 25 50 75 100 125 150 positive slew rate negative slew rate slew rate (v/s) temperature (c) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 -75 -50 -25 0 25 50 75 100 125 150 slew rate (v/s) temperature (c) positive slew rate negative slew rate 0 10 20 30 40 50 60 1 10 100 1k temperature (c) overshoot+ (%) 18v 2.5v 5v 0 10 20 30 40 50 60 1101001k 18v 2.5v 5v temperature (c) overshoot+ (%) -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 0 0.2 1.0 1.2 1.4 1.6 1.8 2.0 v in and v out (v) time(ms) 0.4 0.6 0.8 r l = 10k a v = 1 c l = 7pf v in = 5.9v p-p v s = 5v v in v ou t a t +25 c v ou t a t -55 c v o ut a t +125 c
ISL70219ASEH, isl70419aseh 17 fn8459.0 october 27, 2014 submit document feedback figure 51. 18v positive saturation re covery time (+25c) figure 52. 18v negati ve saturation recovery time (+25c) figure 53. 5v positive saturation re covery time (+25c) figure 54. 5v negati ve saturation recovery time (+25c) typical performance curves unless otherwise specified, v s 18v, v cm = 0, v o = 0v, t a = +25c. (continued) -0.24 -0.20 -0.16 -0.12 -0.08 -0.04 0 0.04 0.08 0 102030405060708090 input voltage level (v) time (s) input +25c -55c +125c -0.08 -0.04 0 0.04 0.08 0.12 0.16 0.20 0.24 0 1020304050607080 90 time (s) input voltage level (v) -55c input +125c +25c -0.28 -0.24 -0.20 -0.16 -0.12 -0.08 -0.04 0 0.04 0 102030405060708090 time (s) input voltage level (v) +125c input +25c -55c -0.04 0 0.04 0.08 0.12 0.16 0.20 0.24 0.28 0 102030405060708090 time (s) input voltage level (v) -55c input +125c +25c
ISL70219ASEH, isl70419aseh 18 fn8459.0 october 27, 2014 submit document feedback post high dose rate radiation characteristics unless otherwise specified, v s 19.8v, v cm =0, v o = 0v, t a = +25c. this data is typical mean test data post radiation expo sure at a high dose rate of 50 to 300rad(si)/s. this data is i ntended to show typical parameter shifts due to high dose rate radiation. these are not limi ts nor are they guaranteed. figure 55. supply current shift vs hdr radiation f igure 56. offset voltage shift vs hdr radiation figure 57. positive input bias current shift vs hdr radiation f igure 58. negative input bias current shift vs hdr radiation figure 59. input offset current shift vs hdr radiation -0.03 -0.02 -0.01 0.00 0.01 0.02 0.03 0 50 100 150 200 250 300 bias gnd krad(si) supply current (ma) -3 -2 -1 0 1 2 3 4 5 6 0 50 100 150 200 250 300 krad(si) offset voltage (v) bias gnd 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0 50 100 150 200 250 300 krad(si) i b+ (na) bias gnd 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0 50 100 150 200 250 300 krad(si) i b- (na) bias gnd -0.10 -0.08 -0.06 -0.04 -0.02 0.00 0.02 0.04 0.06 0.08 0.10 0 50 100 150 200 250 300 gnd bias krad(si) i os (na)
ISL70219ASEH, isl70419aseh 19 fn8459.0 october 27, 2014 submit document feedback post low dose rate radiation characteristics unless otherwise specified, v s 19.8v, v cm =0, v o = 0v, t a = +25c. this data is typical mean test data post radiation exposure at a low dose rate of <10mrad(si)/s. this data is intended to show typical parameter shifts due to high dose rate radiation. these are not limits nor are they guaranteed. figure 60. supply current shift vs ldr radiation figure 61. offset voltage shift vs ldr radiation figure 62. positive input bias current shift vs ldr radiation f igure 63. negative input bias current shift vs ldr radiation figure 64. input offset current shift vs ldr radiation -0.10 -0.08 -0.06 -0.04 -0.02 0.00 0.02 0.04 0.06 0.08 0.10 0 102030405060708090100 supply current (ma) krad(si) gnd biased -15 -10 -5 0 5 10 15 0 102030405060708090100 offset voltage (v) krad(si) gnd biased -15 -10 -5 0 5 10 15 0 102030405060708090100 i b+ (na) krad(si) gnd biased -15 -10 -5 0 5 10 15 0 102030405060708090100 i b+ (na) krad(si) gnd biased -1.00 -0.80 -0.60 -0.40 -0.20 0.00 0.20 0.40 0.60 0.80 1.00 0 102030405060708090100 i os (na) krad(si) gnd biased
ISL70219ASEH, isl70419aseh 20 fn8459.0 october 27, 2014 submit document feedback applications information functional description the ISL70219ASEH and isl70419aseh are dual and quad, low noise precision op amps. these devices are fabricated in a new precision 40v complementary bipolar di process. a super-beta npn input stage with input bias current cancellation provides low input bias current (180pa typical), low input offset voltage (13v typical), low input noise voltage (8nv/ hz), and low 1/f noise corner frequency (~8hz). these amplifiers also feature high open loop gain (14kv/mv) for excellent cmrr (145db) and thd+n performance (0.0005% at 3.5v rms , 1khz into 2k ). a complementary bipolar output st age enables high capacitive load drive without external compensation. operating voltage range the devices are designed to operate across the 4.5v (2.25v) to 40v (20v) voltage range and are fully characterized at 10v (5v) and 36v (18v). the power supply rejection ratio typically exceeds 140db across the full operating voltage range and 120db minimum across the -55c to +125c temperature range. the worst case common mode input voltage range over-temperature is 2v to each rail. with 18v supplies, cmrr performance is typically >130db over-temperature. the minimum cmrr performance across the -55c to +125c temperature range is >120db for power supply voltages from 5v (10v) to 18v (36v). input performance the super-beta npn input pair provides excellent frequency response while maintaining high input precision. high npn beta (>1000) reduces input bias current while maintaining good frequency response, low input bias current and low noise. input bias cancellation circuits pr ovide additional bias current reduction to <5na, and excellent temperature stabilization. figures 6 through 8 show the high degree of bias current stability at 5v and 18v supplies that is maintained across the -55c to +125c temperature range. the low bias current tc also produces very low input offset current tc, which reduces dc input offset errors in precision, high impedance amplifiers. the +25c maximum input offset voltage (v os ) is 85v at 18v supplies. input offset voltage temperature coefficients (v os tc) is a maximum of 1.0v/c. the v os temperature behavior is smooth ( figures 3 through 5 ) maintaining constant tc across the entire temperature range. input esd diode protection the input terminals (in+ and in-) have internal esd protection diodes to the positive and negative supply rails, series connected 500 current limiting resistors and an antiparallel diode pair across the inputs ( figure 65 ). the series resistors limit the high feed-through currents that can occur in pulse applications wh en the input dv/dt exceeds the 0.5v/s slew rate of the amplifier. without the series resistors, the input can forward-bias the antipa rallel diodes causing current to flow to the output resulting in severe distortion and possible diode failure. figure 36 provides an example of distortion free large signal response using a 4v p-p input pulse with an input rise time of <1ns. the series resistors enable the input differential voltage to be equal to the maximum power supply voltage (40v) without damage. in applications where one or both amplifier input terminals are at risk of exposure to high voltages beyond the power supply rails, current limiting resistors may be needed at the input terminal to limit the current through the power supply esd diodes to 20ma maximum. output current limiting the output current is internally limited to approximately 45ma at +25c and can withstand a short circuit to either rail as long as the power dissipation limits are not exceeded. this applies to only 1 amplifier at a time for the dual/quad op amp. continuous operation under these conditio ns may degrade long term reliability. figure 14 shows the current limit variation with temperature. output phase reversal output phase reversal is a change of polarity in the amplifier transfer function when the input voltage exceeds the supply voltage. the ISL70219ASEH and isl70419aseh are immune to output phase reversal, even when the input voltage is 1v beyond the supplies. figure 65. input esd diode current limiting - unity gain - + r l v in v out v + v - 500 500
ISL70219ASEH, isl70419aseh 21 fn8459.0 october 27, 2014 submit document feedback power dissipation it is possible to exceed the +150c maximum junction temperatures under certain load and power supply conditions. it is therefore important to ca lculate the maximum junction temperature (t jmax ) for all applications to determine if power supply voltages, load conditions or package type need to be modified to remain in the safe operating area. these parameters are related using equation 1 : where: ?p dmaxtotal is the sum of the maximum power dissipation of each amplifier in the package (pd max ) ?pd max for each amplifier can be calculated using equation 2 : where: ?t max = maximum ambient temperature ? ? ja = thermal resistance of the package ?pd max = maximum power dissipation of 1 amplifier ?v s = total supply voltage ?i qmax = maximum quiescent supply current of 1 amplifier ?v outmax = maximum output voltage swing of the application t jmax t max ? ja pd maxtotal ? + = (eq. 1) pd max v s i qmax v s ? - v outmax ? v outmax r l ---------------------------- ? + ? = (eq. 2)
ISL70219ASEH, isl70419aseh 22 fn8459.0 october 27, 2014 submit document feedback ISL70219ASEH die characteristics die dimensions 2406m x 2935m (95mils x 116mils) thickness: 483m 25m (19mils 1 mil) interface materials glassivation type: silicon nitride/silicon dioxide sandwich thickness: 15k? top metallization type: alcu (99.5%/0.5%) thickness: 30k? backside finish silicon process pr40 (di) assembly related information substrate potential floating additional information worst case current density < 2 x 10 5 a/cm 2 transistor count 466 weight of packaged device 0.3958 grams (typical) lid characteristics finish: gold potential: unbiased, tied to package pin 6 case isolation to any lead: 20 x 10 9 (min) metallization mask layout outa -ina +ina v- -inb +inb outb v+
ISL70219ASEH, isl70419aseh 23 fn8459.0 october 27, 2014 submit document feedback table 1. ISL70219ASEH die layout x-y coordinates pad name pad number x (m) y (m) dx (m) dy (m) bond wires per pad outb 1 2195.0 1418.0 70 70 1 v + 2 2195.0 2510.0 70 70 1 outa 3 709.0 2727.0 70 70 1 -ina 4 339.0 2727.0 70 70 1 +ina 5 114.0 2510.0 70 70 1 v - 6 114.0 336.0 70 70 1 +inb 7 2195.0 336.0 70 70 1 -inb 8 1970.0 110.0 70 70 1 note: 8. origin of coordinates is the bottom left corner of the die.
ISL70219ASEH, isl70419aseh 24 fn8459.0 october 27, 2014 submit document feedback isl70419aseh die characteristics die dimensions 2406m x 2935m (95mils x 116mils) thickness: 483m 25m (19mils 1 mil) interface materials glassivation type: silicon nitride/silicon dioxide sandwich thickness: 15k? top metallization type: alcu (99.5%/0.5%) thickness: 30k? backside finish silicon process pr40 (di) assembly related information substrate potential floating additional information worst case current density < 2 x 10 5 a/cm 2 transistor count 482 weight of packaged device 0. 6043 grams (typical) lid characteristics finish: gold potential: unbiased, tied to package e-pad case isolation to any lead: 20 x 10 9 (min) metallization mask layout outa r ina +ina +inb r inc +inc v r +ind outc outb r inb v+ r ind outd
ISL70219ASEH, isl70419aseh 25 fn8459.0 october 27, 2014 submit document feedback table 2. isl70419aseh die layout x-y coordinates pad name pad number x (m) y (m) dx (m) dy (m) bond wires per pad outa 3 709.0 2727.0 70 70 1 -ina 4 339.0 2727.0 70 70 1 +ina 5 114.0 2501.0 70 70 1 v + 9 114.0 1419.0 70 70 1 -inb 13 339.0 110.0 70 70 1 +inb 14 114.0 327.0 70 70 1 outb 15 709.0 110.0 70 70 1 outc 16 1600.0 110.0 70 70 1 -inc 17 1970.0 110.0 70 70 1 +inc 18 2195.0 327.0 70 70 1 v - 22 2195.0 1419.0 70 70 1 -ind 26 1970.0 2727.0 70 70 1 +ind 1 2195.0 2501.0 70 70 1 outd 2 1600.0 2727.0 70 70 1 note: 9. origin of coordinates is the bottom left corner of die.
ISL70219ASEH, isl70419aseh 26 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn8459.0 october 27, 2014 for additional products, see www.intersil.com/en/products.html submit document feedback about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastr ucture, mobile computing and high-end consumer markets. for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o the web to make sure that you have the latest revision. date revision change october 27, 2014 fn8459.0 initial release.
ISL70219ASEH, isl70419aseh 27 fn8459.0 october 27, 2014 submit document feedback ceramic metal seal fl atpack packages (flatpack) notes: 1. index area: a notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. the manufacturer?s identification shall not be used as a pin one identification mark. alternately, a tab (dimension k) may be used to identify pin one. 2. if a pin one identification mark is used in addition to a tab, the lim- its of dimension k do not apply. 3. this dimension allows for off- center lid, meniscus, and glass overrun. 4. dimensions b1 and c1 apply to lead base metal only. dimension m applies to lead plating and finish thickness. the maximum lim- its of lead dimensions b and c or m shall be measured at the cen- troid of the finished lead surfac es, when solder dip or tin plate lead finish is applied. 5. n is the maximum number of terminal positions. 6. measure dimension s1 at all four corners. 7. for bottom-brazed lead packages, no organic or polymeric mate- rials shall be molded to the bottom of the package to cover the leads. 8. dimension q shall be measured at the point of exit (beyond the meniscus) of the lead from t he body. dimension q minimum shall be reduced by 0.0015 inch (0.038mm) maximum when sol- der dip lead finish is applied. 9. dimensioning and tolerancing per ansi y14.5m - 1982. 10. controlling dimension: inch. -d- -c- 0.004 h a - b m d s s -a- -b- 0.036 h a - b m d s s e e a q l a e1 seating and l e2 e3 e3 base plane -h- b c s1 m c1 b1 (c) (b) section a-a base lead finish metal pin no. 1 id area a m d k10.a mil-std-1835 cdfp3-f10 (f-4a, configuration b) 10 lead ceramic metal seal flatpack package symbol inches millimeters notes min max min max a 0.045 0.115 1.14 2.92 - b 0.015 0.022 0.38 0.56 - b1 0.015 0.019 0.38 0.48 - c 0.004 0.009 0.10 0.23 - c1 0.004 0.006 0.10 0.15 - d - 0.290 - 7.37 3 e 0.240 0.260 6.10 6.60 - e1 -0.280-7.11 3 e2 0.125 - 3.18 - - e3 0.030 - 0.76 - 7 e 0.050 bsc 1.27 bsc - k 0.008 0.015 0.20 0.38 2 l 0.250 0.370 6.35 9.40 - q 0.026 0.045 0.66 1.14 8 s1 0.005 - 0.13 - 6 m - 0.0015 - 0.04 - n10 10- rev. 0 3/07
ISL70219ASEH, isl70419aseh 28 fn8459.0 october 27, 2014 submit document feedback package outline drawing k14.c 14 lead ceramic metal seal flatpack package rev 0, 9/12 side view top view section a-a -d- -c- seating and base plane -h- base metal pin no. 1 id area 0.022 (0.56) 0.015 (0.38) 0.050 (1.27 bsc) 0.005 (0.13) min 0.115 (2.92) 0.085 (2.16) 0.045 (1.14) 0.026 (0.66) 0.260 (6.60) 0.248 (6.30) 0.009 (0.23) 0.004 (0.10) 0.370 (9.40) 0.270 (6.86) 0.03 (0.76) min 0.006 (0.15) 0.004 (0.10) 0.009 (0.23) 0.004 (0.10) 0.019 (0.48) 0.015 (0.38) 0.0015 (0.04) max 0.022 (0.56) 0.015 (0.38) 3 5 2 lead finish 1. adjacent to pin one and shall be located within the shaded area shown. the manufacturer?s identification shall not be used as a pin one identification mark. 2. the maximum limits of lead dimensions (section a-a) shall be measured at the centroid of the fi nished lead surf aces, when solder dip or tin plate lead finish is applied. 3. 4. shall be molded to the bottom of the package to cover the leads. 5. meniscus) of the lead from the body. dimension minimum shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied. 7. 8. notes: dimensioning and tolerancing per ansi y14.5m - 1982. dimensions: inch (mm). controlling dimension: inch. index area: a notch or a pin one identification mark shall be located measure dimension at all four corners. for bottom-brazed lead packages, no organic or polymeric materials dimension shall be measured at the point of exit (beyond the 0.390 (9.91) 0.376 (9.55) 0.183 (4.65) 0.167 (4.24) 6 bottom metal 6. the bottom of the package is a solderable metal surface. bottom view optional pin 1 index bottom metal 0.005 (0.127) ref. offset from ceramic edge a a 1

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